Undergraduate Teaching 2017-18

Engineering Tripos Part IIA, 3B2: Integrated Digital Electronics, 2017-18

Engineering Tripos Part IIA, 3B2: Integrated Digital Electronics, 2017-18

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Leader

Dr D Popa

Lecturers

Dr D Popa and Dr O Akan

Lab Leader

Dr O Akan

Timing and Structure

Lent term. 16 lectures.

Aims

The aims of the course are to:

  • Introduce key aspects of integrated digital electronics and its applications as logic devices.
  • Introduce design and optimization techniques for combinational and sequential digital logic circuits.
  • Introduce programmable logic design and hardware description language (VHDL) concepts.
  • Introduce the principles of design and operation of the major digital integrated circuit technologies.
  • Discuss the importance of miniaturising digital circuits and their key role in microprocessors, memories and programmable logic devices.

Objectives

As specific objectives, by the end of the course students should be able to:

  • Understand the technologies that serve as building blocks to modern digital circuits and know their main applications.
  • Analyse and synthesise how LSI circuits are used in logic; Multiplexers, Read-only Memories, Programmable Logic Devices (PLDs).
  • Design sequential logic circuits and finite state machines, and know about the Moore and Mealy models.
  • Be familiar with VHDL hardware description language and be able to write code for basic circuits.
  • Design synchronous circuits and use complex PLDs for design of sequential networks.
  • Be familiar with the architecture and programming of modern FPGA devices and the design flow involved.
  • Appreciate the drive to miniaturise digital circuits and understand how this has improved performance and reduced cost.
  • Know the definitions for noise margins, rise times, fall times and transfer characteristics for digital circuits.
  • Be aware of the two operating regions (saturation and non-saturation) of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and understand how the equations for the two regions are used to design and estimate the performance of digital circuit
  • Appreciate the evolution of MOSFET inverters from the resistive load inverter through the enhancement and depletion transistor load inverters to the CMOS inverter.
  • Plot the transfer characteristics and calculate the rise times for NMOS and CMOS inverters.
  • Know the basic gate circuits for NMOS and CMOS logic and be able to compare their performance.
  • Distinguish between the cut-off, linear and saturation regions of the bipolar transistor and know how the Ebers-Moll equations are used to design and estimate the performance of bipolar transistor digital circuits.
  • Explain charge storage in diodes and bipolar transistors and understand how it limits the switching speed of bipolar digital circuits.
  • Explain the operation of bipolar/CMOS (BiCMOS) circuits and be aware of their advantages for fast logic gates.
  • Explain the operation of Emitter Coupled Logic (ECL) logic circuits and be able to plot the transfer characteristic and calculate the risetime for an ECL inverter.
  • Understand the operation of the MOS Schmitt trigger and be able to calculate the trigger voltages.
  • Understand the operating principles and design challenges of static and dynamic memories.

Content

Logic Circuits (8L)

Lecture 1. Introduction to logic circuits
Revision of Boolean algebra. NAND, NOR synthesis and logic networks.

Lecture 2. Introduction to VHDL
Introduction to CAD tools. VHDL terminology, modeling, synthesis. Design units.

Lecture 3. Combinational circuits
Multiplexers, ROMs, Programmable logic devices (PLDs). 7-digit display example.

Lecture 4. Sequential circuits
Mealy and Moore models. Design steps. Counter example.

Lecture 5. Practical example of a sequential network
Hierarchical design with VHDL.

Lecture 6. Complex combinational/sequential circuits
Complex PLDs. Logic block features. Programmable macrocells.

Lecture 7. Field programmable gate array architecture
Lookup tables, routing, I/O, clock. Programming.

Lecture 8. Digital signal processing
Fast Fourier transform (FFT) demo board application.

Digital Circuits (8L)

Lecture 1. Introduction to digital microelectronics

Lecture 2. Logic gate definitions
Inverter transfer characteristics, noise margins, rise times, fall times, delay times, etc. (H & J, Chap. 1).

Lecture 3. MOS Transistors
(H & J, Chap. 2).

Lecture 4. MOS and CMOS Inverters
(H & J Chap. 3).

Lecture 5. Bipolar Transistors and charge storage
(H & J Chap. 4).

Lecture 6. ECL
(H & J, Chap. 7).

Lecture 7. BiCMOS gates. Schmitt triggers
(H & J, Chapter 8).

Lecture 8. Semiconductor memories: static and dynamic RAM circuits
(H & J, Chapter 9).

Coursework

FPGA Experiment

Students are provided with a Field Programmable Gate Array (FPGA) board and are asked to design a basic logic circuit, described by VHDL code, and use it to configure the FPGA chip. The circuit implementation is used to test the FPGA board functionality and understand the versatility of programmable logic technology.

Learning objectives

  • Gain experience with FPGA devices
  • Analyze and design logic circuits using VHDL
  • Learn a design-flow for FPGAs
  • Configure designed circuits into FPGAs
  • Test configured FPGA devices

Practical information:

  • Sessions will take place in EIETL, during weeks 1-8 Lent term.
  • This activity involves preliminary work (~2h). You are required to read the lab handouts before lab sessions, and perform any activity required by the Lab Leader as a preparation for the lab.

Full Technical Report:

Students will have the option to submit a Full Technical Report.

 

Booklists

Please see the Booklist for Part IIA Courses for references for this module.

Examination Guidelines

Please refer to Form & conduct of the examinations.

Last modified: 08/02/2018 16:21