Aims

The aims of the course are to:

• practise digital system modelling techniques using Verilog HDL
• obtain hands-on experience working with FPGAs and their synthesis tools
• explore fundamental concepts in computer architecture through the study and implementation of RISC-V instruction set architecture (ISA)
• perform evaluation and verification of a microprocessor core on FPGAs, in a team environment

Objectives

As specific objectives, by the end of the course students should be able to:

• model digital systems effectively using the Verilog hardware description language
• use design tools for FPGAs for synthesis, simulation and programming
• comprehend a simple microprocessor design and realise improvement in performance, power or area
• systemically evaluate and verify a microprocessor

Content

In this project, the students will be working on improving a simple RISC-V processor in terms of performance, power or area when it is implementation on an iCE40 FPGA. For the first two weeks, the students will be investigating the available hardware resources on the FPGA and learning to model and map a digital system using the Verilog HDL. Then they will be guided to explore the basics of computer architecture through studying the given processor. They will also practise evaluating of the processor implementation for the performance, power and area. In the second half, the groups of three students have the liberty to identify and realise possible improvements for the processor core. For example, pipelining, caching, out-of-order execution, co-processing units are popular options for high performance processors. They will propose, implement, verify and evaluate their improvement and detail the process in the report.

This project will provide you with the opportunity to gain hands-on experience with FPGA, HDL modelling, computer architecture.

Week 1

Introduction to the project. FPGA device and design tools. Measurements with FPGA. 

Week 2

Basic computer architecture. RISC-V software tool chain. FPGA implementation of RISC-V processor. Baseline measurements/records.

Week 3

Discussion and proposal of ideas. Preliminary study and implementation. Debugging.

Week 4

Finalised core improvement. Verification, evaluation and optimisation.

Aims

The aims of the course are to:

• To become familiar with Verilog HDL and with the Lattice iCE40, a state-of-the-art low-power miniature FPGA used in many commercial embedded sensing and wearable computing applications.
• To obtain experience working with FPGA synthesis tools for embedded sensing and computing applications.
• To gain experience with the RISC-V (pronounced "RISC-five") architecture, an exciting, new, and forward-looking reduced instruction set computer (RISC) architecture.
• To carry out the implementation and evaluation of a minimal subset of the RISC-V architecture on the iCE40 FPGA.

Content

Students will work in groups of three for this project.

Students modify an unoptimized RV32I RISC-V processor running on an iCE40 FPGA in a tiny wafer-scale 2.15x2.50 mm WLCSP package, using a completely open-source toolchain. The hardware used in the project has isolated power rails for the FPGA core, I/O, and PLL. Because the hardware has built-in shunt resistors, students can measure power usage with a laboratory multimeter. Students work in groups of three to evaluate the performance, power dissipation, and resource usage of their modifications and the project culminates in a competition between teams to achieve designs on the Pareto frontier. (One team last year got active power dissipation, while running a provided benchmark, down to 214 microwatts.)

The RISC-V architecture is a new open reduced instruction set computer (RISC) architecture that has many advantages over legacy architectures such as ARM. Because it was designed from the ground up for efficiency, RISC-V enables more efficient hardware implementations than many existing commercial architectures. One variant of the RISC-V is small enough to fit within the Lattice iCE40, a low-power miniature FPGA (in a 2.15x2.55mm package) targeted at embedded sensing systems. This project will provide students with the opportunity to gain experience with the RISC-V architecture, an exciting, new, and forward-looking reduced instruction set computer (RISC) architecture and to implement and evaluate a minimal subset of the RISC-V architecture on the iCE40 FPGA.

Week 1

Complete the warm-up exercise mapping the provided pre-implemented RISC-V subset processor core on the iCE40 and become familiar with the open-source FPGA synthesis tools, with the RISC-V processor emulator, and with Verilog. Watch the overview fascicle videos on the toolchain and on a Bayesian view of measurements, measurement uncertainty, sensors, and computing on sensor data.

Week 2

Evaluate design options to improve performance, FPGA resource usage, and power dissipation of the baseline RISC-V processor core.

Week 3

Keeping in mind the goal of Pareto-optimal designs, the three team members implement improvements to the performance, power dissipation, and resource usage of the baseline RISC-V processor.

Week 4

Evaluate the improved design in terms of performance, power dissipation, and FPGA resource usage for the measurement data uncertainty propagation and particle filter benchmark applications.