Undergraduate Teaching 2024-25

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Engineering Tripos Part IIB, 4M29: Designed to Lead, 2024-25

Leader

Ms K Lanucha

Timing and Structure

Michaelmas term. 100% coursework

Prerequisites

None

Aims

The aims of the course are to:

  • Developing essential leadership competencies through reflecting, exchanging ideas, and holding each other accountable for progress.

Objectives

As specific objectives, by the end of the course students should be able to:

  • Enhance adaptability and resilience as a leader in the face of volatility, uncertainty, complexity, and ambiguity.
  • Increase self-awareness and recognise the impact of emotions on leadership effectiveness.
  • Develop skills to manage and regulate emotions in oneself and others.
  • Enhance empathy and interpersonal relationships to foster a positive work environment.
  • Understand the key elements of a high performing team and their importance.
  • Acquire fundamental coaching techniques to support the growth and development of individuals.
  • Learn effective questioning and active listening skills to facilitate self-discovery and problem-solving.
  • Understand the importance of diversity and inclusion in leadership and its impact on team performance.
  • Learn strategies to create an inclusive work environment that values and leverages diverse perspectives.
  • Develop skills to build strong relationships and networks to support successful influence.

Content

The consists of a series of 7 seminars spread over a trimester.

Designed to Lead

One 2-hour weekly seminar for 7 weeks

 

Week 1 - Introductory session 

In our opening week, students will dive into the fundamentals of the course, providing them with a roadmap, essential information about designing their development plan, and engaging ice-breakers to set the tone for a collaborative and enriching learning experience.

 

Week 2- Leadership skills for VUCA (volatile, uncertain, complex and ambiguous work environment) 

This session will be focusing on a deep exploration of leadership skills tailored for the VUCA world—where volatility, uncertainty, complexity, and ambiguity reign. Focus: the essential skillset required to navigate and lead in this dynamic global environment, where adaptability is the only certainty.

 

Week 3 - Emotional intelligence

This session invites students to explore the realm of emotional intelligence, help them uncover the nuances of understanding oneself and cultivating robust relationships with team members. Students will reflect on their individual work preferences, explore diverse communication styles, and harness empathy to construct bridges between colleagues.

 

Week 4 - Culture of high performing teams 

This session will be focusing on the dynamics of high-performing teams. Students will delve into the key characteristics that define success, with a particular focus on psychological safety. Focus: understanding the pivotal role leaders play in fostering an environment of safety, vulnerability, and shared goals.

 

Week 5 - Coaching skills

This session will be focusing on how to develop coaching skills to support team members' growth and development. Students will learn about the GROW model of coaching (Goal, Reality, Options, Will. Students will hone their abilities in active listening, master questioning techniques, and refine their feedback.

 

Week 6 - Inclusive leadership

This session introduces the importance of inclusive leadership. Students will reflect on the business case for cognitive diversity and explore strategies to cultivate an inclusive workplace culture. This session will equip them with the skills to champion diversity and promote an environment where everyone's voice is heard.

 

Week 7 - Influencing skills

In this session, the focus will be on the power of influence. Students will sharpen their skills with a focus on confident body language, both online and in-person. They will learn about the subtleties of non-verbal and paraverbal communication to enhance their ability to inspire and others.

 

Week 8 – Individual sessions

Examples papers

N/a

Coursework

The module is assessed using a reflective portfolio.

In the first seven weeks of the module, students must submit seven reflective pieces (between 200 and 300 words each week) on Moodle (in an OU blog).

In week 8, students must submit a development plan (800-1000 words) as an assignment via Moodle. For the assignment, students will need to:

1. Reflect on their learning from the course. This can be done using a model such as Gibbs’ Reflective Cycle. Details on this model and how it can be applied will be provided in class.

2. Drawing from the above, students will identify how to apply the learning by drafting their development plan. This plan needs to outline the key areas they have identified for development, explain why they are of personal benefit and define specific, measurable, achievable, relevant and time-bound (SMART) actions to achieve their goals.

 

 

Examination Guidelines

Please refer to Form & conduct of the examinations.

 
Last modified: 07/06/2024 10:50

Engineering Tripos Part IIB, 4B28: Very large-scale integration (VLSI), 2024-25

Leader

Dr M Tang

Lecturer

Dr M Tang

Timing and Structure

Michaelmas term. 75% exam / 25% coursework

Prerequisites

3B2 assumed, 3B5 useful.

Aims

The aims of the course are to:

  • provide fundamental knowledge and analytical skills required for VLSI systems design in the nanometre era
  • illustrate the importance of custom design tools and also electronic design automation (EDA) for physical implementation, testing and verifications of VLSI systems

Objectives

As specific objectives, by the end of the course students should be able to:

  • be familiar with the modern CMOS fabrication process, physical layout design rules and anticipate trends in VLSI fabrication technologies
  • understand the trade-off between the four key design metrics of modern VLSI systems – cost, reliability, speed and power
  • recognise the parasitic effect of wires/interconnects and apply wire delay models like lumped RC model and Elmore delay model
  • understand the sources of power dissipation and the factors affecting robustness of a VLSI system
  • design and optimise multi-level CMOS combinational and sequential circuits using static logic, pass transistor logic and dynamic logic
  • operate up-to-date design tools for VLSI systems and evaluate the quality of the outputs (e.g. floorplan, routing, physical layout, etc.)

Content

The module will introduce the design principles of integrated circuit designs with millions of digital devices. It begins with CMOS design flows and fabrication processes that creates modern VLSI and explains the design metrics (performance, power, cost, reliability). The typical combinational and sequential circuit design styles like static logic, pass transistor logic and dynmaic logic will be illustrated with many examples of digital devices. The effect of wires and interconnects on circuit speed and power will be studied. The module will be concluded with a case study of cutting-edge advanced VLSI technologies (e.g. FinFET) and design techniques.

Design Flow and Metrics (1L)

  • Design flow: design, synthesis, planning, implementation, fabrication
  • Cost: yield and detects of wafer die
  • Reliability: noise margins, regenerative property of digital circuits
  • Speed: delay definition, Fanout-of-four (FO4) delay
  • Power: instantaneous, average, peak

CMOS Fabrication and Layout Design Rules (1L)

  • Fabrication process: substrate preparation, photolithography, doping and diffusion, oxidation, packing
  • Design rules: micron rules vs scalable rules, CMOS process layers, stick diagrams (sketch)

CMOS Combinational Circuits, Pass Transistor Logic, Dynamic Logic (2L)

  • Static complementary CMOS logic, progressive transistor sizing
  • Ratioed logic, e.g. pseudo-NMOS
  • Pass transistor logic: threshold drop, level restorer, transmission gate
  • Dynamic logic: charge leakage, charge sharing, clock feedthrough, backgate coupling, domino logic

Wires and Interconnects (2L)

  • Interconnect parameters: capacitance, resistance and inductance
  • Wire models: lumped model, lumped RC model, Elmore delay model
  • Distributed RC line

Power and Robustness (1L)

  • Dynamic power disspation
  • Static comsumption
  • Power analysis and optimisation technique
  • Signal integrity issues

Logical Effort (1L)

  • Delay of logic gates
  • Derivation of intrinsic delay and logic effort
  • Optimisation for buffer sizing and the number of buffer stages
  • Branching Effort

I/O and Electrostatic Discharge Protection (1L)

  • Input and output (I/O) pad and buffer design
  • Tri-state buffers

CMOS Sequential Circuit Design, Clocking (2L)

  • Static latches, flip-flops, and registers
  • Dynamic designs: C2MOS register and TSPC latch
  • Clock tree and clocking strategies

Advanced VLSI Technology and Design Techniques (e.g. FinFET, 3D stacking) (1L)

  • Topics varies every year, suggestions from students are welcome.

Coursework

Students are provided with the specification of a custom cell, and a reference design in hardware description language (VHDL), for instance a multiplier-accumulator (MAC) circuit. They will be asked to design the cell using the layout editor and verify its correctness via device extraction and SPICE simulation. The custom cell will then be used in junction with other standard cells in the SKY130 (180nm - 130nm) Process Design Kit (PDK). During the process, they will be instructed to inspect and analyse the generated results and reports from the various design automation tools. Finally, they will verify the final physical layout of the reference design using SPICE simulations.

This activity involves preliminary work (~2h). You are required to read the lab handouts before lab sessions and be familiar with the usage of various design tools for this activity.

A total of 16 hours (including preliminary work) is required to complete this coursework.

Students will have the option to submit a Full Technical Report.

Submission and Assessment

The student will be asked to submit -

  • the layout of the custom cell and the extracted SPICE file (25%)
  • plots of SPICE simulations that verify the custom cell layout and the reference design (50%)
  • a piece of reflective writing on the individual lab experience (25%)

Learning Objectives:

  • Gain experience with VLSI/ASIC design tools (e.g. Cadence design tools)
  • Learn to create layout for a custom cell design and extract device characteristics for SPICE simulations
  • Practise a semi-custom design flow for VLSI/ASIC
  • Verify a physical design

Booklists

  • (Core) Analysis and design of digital integrated circuits: in deep submicron technology, David A. Hodges, Horace G. Jackson, Resve A. Saleh., 3rd ed, ISBN: 0072283653
  • (Recommended) Rabaey, Chandrakasan and Nikolic, Digital Integrated Circuits, 2nd ed, ISBN-13: 978-0130909961
  • (Recommended) Weste and Harris, CMOS VLSI Design, 4th ed, ISBN-13: 978-0321547743

 

Examination Guidelines

Please refer to Form & conduct of the examinations.

 
Last modified: 11/06/2024 19:45

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